The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, particularly to a semiconductor device including a CMOS transistor (CMOS) in which a channel layer includes a strained layer and a method of manufacturing the same.
In semiconductor devices, particularly CMOS devices, there have been conducted enhancement of drive capability and reduction in power consumption from the viewpoint of enhancing the performance of the devices, and these developments have been made by thinning the gate insulation film and miniaturizing the gate structure. However, due to the conspicuous tendencies toward an increased leak current, a short channel effect and the like; it has been becoming difficult to enhance the drive capability by simple miniaturization.
In view of this, in recent years, for enhancing the device performance, a trial to utilize a heterostructure of silicon (Si) and silicon-germanium (SiGe) has been made. For example, it is known that when, to enhance the speed of an NMOS transistor (NMOS), a mixed crystal layer of Si and germanium (Ge) larger in lattice constant than Si is grown on an Si substrate, thereby forming a relaxed SiGe layer in a lattice relaxed state, then a strained Si layer in a tension-strained state is formed thereon, and a channel region is formed in the strained Si layer, the carrier mobility (electron mobility) in the channel region is enhanced. It is also known that when, in order for example to enhance the speed of a PMOS transistor (PMOS), a strained SiGe layer in a compression-strained state is formed on an Si substrate, and a channel region is formed in the strained SiGe layer, the carrier mobility (hole mobility) in the channel region is enhanced.
Based on the above, an example of CMOS device has been reported in which a strained Si layer is used as the NMOS channel region and a strained SiGe layer is used as the PMOS channel region. Such a CMOS device has been manufactured by a method in which a relaxed SiGe layer, a strained Si layer and a strained SiGe layer are laminatingly formed on an Si substrate, the strained SiGe layer is removed and the strained Si layer is removed to a certain level of depth in the NMOS region, thereby exposing the strained Si layer having a high coefficient of straining, then the channel region of the NMOS transistor is formed in the strained Si layer thus exposed, and the channel region of the PMOS transistor is formed in the strained SiGe layer, to manufacture the CMOS device (see, for example, Japanese Patent Laid-open No. Hei 10-93025).
On the other hand, it has been reported that in NMOS, the electron mobility is higher in the order (100)>(111)>(110) in terms of the plane orientation of the surface of the Si substrate, whereas in PMOS, the hole mobility is higher in the order of (110)>(111)>(100) in terms of the plane orientation of the surface of the Si substrate (See M. Yang et al, “IEEE Electron Device Letters” (USA), 2003, Vol. 24, p. 339, for example).